1. Field of the Invention
The invention relates to a variable voltage tolerant input/output circuit, and more particularly, to a variable voltage tolerant input/output circuit that produces no leakage current.
2. Description of Related Art
Owing to the constant miniaturization of integrated circuits by advanced fabrication techniques, the supply voltage of a single chip has to be lowered continuously to maintain the stable and reliable operational characteristics of the integrated circuits. The power consumption is reduced in such manner and the circuit speed is also improved. Certain types of products, due to present fabrication techniques, need to operate within comparatively higher voltage ranges, thereby resulting in different integrated circuits on a same printed circuit board sharing the same data bus while using different supply voltages. When the difference between the data bus voltage produced by an integrated circuit with high supply voltage and an integrated circuit with low supply voltage gets too large, the data bus voltage is distorted and the power consumption of the integrated circuit gets too large as well, and therefore normal functioning and operation may not be brought into full play.
FIG. 1 shows a conventional single voltage input/output circuit, which includes PMOS transistors M1, M3 and M5, and NMOS transistor M2, M4 and M6. The gates of M3 and M4 are coupled to an input control signal PU, the gates of M5 and M6 are coupled to another input control signal PD, the drain of M2 is coupled to an output circuit, one P+ region of M1 is coupled via an electrode to the output circuit, while the other P+ region is coupled via an electrode to the supply voltage VCC, the sources of M3 and M5 are coupled to the supply voltage VCC, the sources of M2, M4 and M6 are coupled to the ground voltage VSS, the drains of M3 and M4 are coupled to the gate of M1, and the drains of M5 and M6 are coupled to the gate of M2.
The leakage current problem of the conventional input/output circuit shown in FIG. 1 is discussed below in two circumstances:
(1) When the logic high voltage of the input/output circuit voltage VI/O is lower than the supply voltage VCC (for example, VI/O=3V and VCC=5V), and M1 and M2 are in an OFF state, the N-well voltage of M1 is VCC. As a result of the input/output voltage being lower than the N-well voltage of M1, a forward diode leakage current is non-existent between the P+ region and the N-Well of M1.
(2) When the logic high voltage of the input/output circuit VI/O is higher than the supply voltage VCC (for example, VI/O=5V and VCC=3V), and M1 and M2 are in an OFF state, the N-well voltage of M1 is VCC. Therefore, a forward diode leakage current exists between the P+ region and N-well of M1, as shown in FIG. 2. The leakage current has a critical effect on the normal operation of M1.
In other words, when the logic high voltage of the input/output voltage VI/O is higher than the supply voltage VCC, the leakage current problem is unavoidable. The leakage current then causes dissipation difficulties, which get more distinct when there are a bulky data bus and large difference between the data voltage and the supply voltage.
In the view of the above, an object of the invention is to provide a variable voltage tolerant input/output circuit that produces no leakage current.
Another object of the invention is to provide a variable voltage tolerant input/output circuit with high reliability.
To achieve the above objects, the variable voltage tolerant input/output circuit of the invention includes: a supply voltage; a first PMOS transistor, with one of its P+ regions coupled via an electrode to the supply voltage while the other P+ region coupled via an electrode to an output circuit; a second PMOS transistor, with one of its P+ regions coupled via an electrode to the supply voltage while the other P+ region coupled via an electrode to the gate of the first PMOS transistor, and its gate coupled to an input control circuit; a third PMOS transistor, with its source coupled to the supply voltage and its gate coupled to another input control circuit; a first NMOS transistor, with its drain coupled to the output circuit, its source coupled to the ground voltage, and its gate coupled to the drain of the third PMOS transistor; a second NMOS transistor, with its drain coupled to the gate of the first PMOS transistor, its source coupled to the ground voltage, and its gate coupled to the gate of the second PMOS transistor; a third NMOS transistor, with its drain coupled to the gate of the first NMOS transistor, its source coupled to the ground voltage, and its gate coupled to the gate of the third PMOS transistor.
The circuit further includes a clamping circuit which includes:
a fourth PMOS transistor, with its gate coupled to the N-well of the first PMOS transistor, one of its P+ regions coupled via an electrode to the supply voltage while the other P+ region coupled via an electrode to the N-well of the first PMOS transistor; a fifth PMOS transistor, with its gate coupled to the N-well of the first PMOS transistor, one of its P+ regions coupled via an electrode to the N-well of the PMOS transistor while the other P+ region coupled via an electrode to the output circuit. The P+ region of the second PMOS transistor originally coupled via an electrode to the supply voltage is replaced by the N-well coupled via an electrode to the first PMOS transistor.
By means of the variable voltage tolerant input/output circuit design provided by the invention, it is made sure that the data bus voltage is not distorted due to large difference between it and the integrated circuit voltage, and the problem of being unable to function and operate normally due to excessive power consumed by the integrated circuit is also overcome.